Generally, semiconductor devices can be classified into a lateral semiconductor device, where its electrodes are formed on one major surface of the device, and a vertical semiconductor device, where its electrodes are distributed onto both of its major surfaces facing opposite to each other. In the vertical semiconductor device, the direction of the drift current flow in its ON-state coincides with the direction of the expansion of the depletion layer caused by a reverse bias voltage in its OFF-state. In the typical planar-type n-channel vertical MOSFET, its high resistive portion formed of an n−-type drift layer works as a region in which the drift current is made to flow substantially vertically in the ON-state of the MOSFET. Since the drift resistance is reduced by shortening the current path in the n−-type drift layer, the on-resistance of the planar-type n-channel vertical MOSFET is reduced.
The high resistive portion is depleted in the OFF-state to raise the breakdown voltage of the MOSFET. As the n−-type drift layer is thinner, the width of the depletion layer expanding from the pn-junction between a p-type base region and an n−-type drift layer becomes narrower. Accordingly, the electric field strength reaches the critical electric field strength of silicon sooner, lowering the breakdown voltage. In contrast, the n−-type drift layer needs to be thick in the semiconductor device exhibiting a high breakdown voltage to increase the on-resistance thereof, resulting in large loses. Thus, there exists a tradeoff relation between the on-resistance and the breakdown voltage.
It is well known that the tradeoff relation between the on-resistance and the breakdown voltage exists also in the IGBTs, bipolar transistors, diodes, and similar semiconductor devices. The tradeoff relation between the on-resistance and the breakdown voltage exists also in the lateral semiconductor devices, where the direction of the drift current flow in its ON-state does not coincide with the direction of the expansion of the depletion layer caused by a reverse bias voltage in its OFF-state.
Superjunction semiconductor devices, which include an alternating conductivity type drift layer formed of heavily doped n-type drift regions and heavily doped p-type partition regions arranged alternately, are known to be effective for reducing the tradeoff relation. See for instance U.S. Pat. Nos. 5,216,275 and 5,438,215, and Japanese patent publication JP PHei. 9(1997)-266311A. Even when the alternating conductivity type drift layer is doped heavily, the semiconductor device having the structure described above obtains a high breakdown voltage, as the depletion layers expand laterally from the pn-junctions extending vertically, to the direction of the alternate arrangement of the constituent regions, depleting the entire drift layer.
For realizing a semiconductor device exhibiting a high breakdown voltage, it is necessary to provide the semiconductor device with a peripheral structure. If the semiconductor device is not provided with any peripheral structure, it will be difficult to realize a high breakdown voltage, since the breakdown voltage is low in the peripheral portions of the semiconductor device. For obviating the problems described above, it has been proposed to arrange an alternating conductivity type layer in the surface portion of the peripheral section around the alternating conductivity type layer in the active section of the device. The alternating conductivity type layer in the peripheral section is formed of n-type regions and p-type regions arranged alternately at a pitch that is narrower than the pitch of the n-type regions and p-type regions arranged alternately in the alternating conductivity type layer in the active section. See for instance Japanese patent publications JP P2003-224273A and JP P2004-22716A. The proposed structure relaxes the surface electric field near the active section of device to maintain a high breakdown voltage.
For improving the avalanche withstanding capability of the drift layer in the superjunction semiconductor device, a structure that improves the negative resistance formed during the avalanche breakdown has been proposed. See for instance Japanese patent publication JP P2004-72068A. Moreover, a structure that includes an n−-type drift layer between a layer with a low electrical resistance and an alternating conductivity type layer is known. The n−-type drift layer is doped more lightly than the n-type drift regions in the alternating conductivity type layer. See for instance Japanese patent publication JP P2003-273355A.
FIGS. 23-25 illustrate a conventional vertical MOSFET. FIG. 23 shows a quarter of the drain drift section (the active section of the device). Here, the vertical MOSFET includes an n+-type drain layer (contact layer) 11 having low electrical resistance on the lower surface side of the semiconductor chip. A drain electrode 18 is in electrical contact with the n+-type drain layer 11. A vertical drain drift section 22, which includes a first alternating conductivity type layer 22a, 22b, is on the n+-type drain layer 11. Heavily doped p-type base regions (p-type wells) 13a working as an active section of the device are formed selectively in the surface portion of the vertical drain drift section 22. A heavily doped n+-type source region 14 is formed selectively in the surface portion of the p-type base region 13a. A gate electrode layer 16 made of polysilicon is above the semiconductor chip with a gate insulator film 15 interposed between the gate electrode layer 16 and the semiconductor chip. A source electrode 17 in electrical contact commonly with the p-type base regions 13a and the n+-type source regions 14 via contact holes bored through an interlayer insulator film 19a is formed above the chip. The n+-type source region 14 is formed shallowly in the p-type base region 13a shaped as a well such that a double-diffusion-type MOS section is formed. A p+-type contact region 26 is in the p-type base region 13a. Although not illustrated, a metal film gate wiring is in electrical contact with gate electrode layer 16.
The vertical drain drift section 22 coincides almost with the portion of the semiconductor chip beneath a plurality of p-type base regions 13a working as the active section. The vertical drain drift section 22 includes the first alternating conductivity type layer formed first n-type regions 22a and first p-type regions 22b arranged alternately at a pitch P1 repeating along the major surfaces of the semiconductor chip such that the first n-type regions 22a and the first p-type regions 22b extend parallel to each other along the thickness direction of the semiconductor chip. The upper ends of some first n-type regions 22a reach sandwiched regions 12e, which is above the region between the p-type base regions 13a and the lower ends of the first n-type regions 22a contacting the n+-type drain layer 11. The first n-type regions 22a reaching the sandwiched regions 12e work as current path regions in the ON-state of the MOSFET. The other first n-type regions 22a do not quite work as current path regions. The first p-type regions 22b contact the well bottoms of the p-type base regions 13a at the upper ends thereof and with the n+-type drain layer 11 at the lower ends thereof.
A peripheral section 30 around the drain drift section 22 includes a second alternating conductivity type layer 30a, 30b continuous with the first alternating conductivity type layer in drain drift section 22. The second alternating conductivity type layer is formed of second n-type regions 30a and second p-type regions 30b arranged alternately at a pitch P1 repeating along the major surfaces of the semiconductor chip such that the second n-type regions 30a and the second p-type regions 30b extend parallel to each other along the thickness direction of the semiconductor chip. The pitches of the first and second alternating conductivity type layers are substantially the same. The impurity concentrations of the first and second alternating conductivity type layers also are substantially the same.
A third alternating conductivity type layer is formed in the surface portion of the peripheral section 30. The third alternating conductivity type layer is formed of third n-type regions 34a and third p-type regions 34b arranged alternately at a pitch P2 repeating along the upper surface of the semiconductor chip such that the third n-type regions 34a and the third p-type regions 34b also extend parallel to each other along the thickness direction of the semiconductor chip. The impurity concentrations in the third alternating conductivity type layer are lower than the impurity concentrations in the second alternating conductivity type. The pitch P2 is narrower than the pitch P1.
An oxide film (insulator film) 33 is on the third alternating conductivity type layer. The oxide film 33 becomes thicker stepwisely from the drain drift section 22 to the peripheral section 30 and covers the third alternating conductivity type layer. A field plate electrode FP extends from the source electrode 17 onto the oxide film 33. An n-type channel stopper region 50 in contact with the n+-type drain layer 11 is formed around the peripheral section 30. A stopper electrode 51 is on the n-type channel stopper region 50. The stopper electrode 51 is in electrical contact with the n-type channel stopper region 50.
Although the previously mentioned Japanese patent publication JP 2003-224273A discloses the techniques for obtaining a low on-resistance and a high breakdown voltage, it does not describe anything on the avalanche withstanding capability (breakdown current). The previously mentioned Japanese patent publication JP 2004-72068A does not disclose any structure for improving the negative resistance formed during the avalanche breakdown even if the peripheral section of the device is disclosed. Even when the avalanche withstanding capability in the active section of the device is improved, it will be difficult to secure and guarantee the avalanche withstanding capability of the entire device, if the avalanche withstanding capability in the peripheral section of the device is not improved.
The present inventors have conducted simulations on the current vs. voltage characteristics of the peripheral and active sections in the avalanche breakdown of a vertical MOSFET of the 600 V class having the structure shown in FIGS. 23-25. The sizes and the impurity concentrations of the constituent portions of the alternating conductivity type layers used for the simulations are as follows. The thickness (in the depth direction) of the drain drift section 22 is 44.0 μm. The first n-type region 22a and the first p-type region 22b each are 8.0 μm in width so that the pitch P1 becomes 16.0 μm. The impurity concentration in the first n-type region 22a and the first p-type region 22b is 2.4×1015 cm−3. The thickness (in the depth direction) of the second alternating conductivity type layer in the peripheral section 30 is 31.0 μm. The second n-type region 30a and the second p-type region 30b each are 8.0 μm in width so that the pitch P1 at the second alternating conductivity type layer remains at 16.0 μm. The impurity concentration in the second n-type region 30a and the second p-type region 30b is 2.4×1015 cm−3. The thickness (in the depth direction) of the third alternating conductivity type layer in the peripheral section 30 is 13.0 μm. The third n-type region 34a and the third p-type region 34b each are 4.0 μm in width so that the pitch becomes 8.0 μm. The impurity concentration in the third n-type region 34a and the third p-type region 34b is 4.8×1014 cm−3.
FIGS. 26-28 are graphs describing the simulation results in the portion along the line segment XXIV-XXIV of FIG. 23. Considering the impurity concentration variations, the impurity concentration Nn in the n-type regions is set to be lower by 10% than the impurity concentration Np in the p-type regions in FIG. 26, the impurity concentration Nn in the n-type regions is set to be equal to the impurity concentration Np in the p-type regions in FIG. 27, and the impurity concentration Nn in the n-type regions is set to be higher by 10% than the impurity concentration Np in the p-type regions in FIG. 28. FIGS. 26-28 indicate that there exists a negative resistance region in the current vs. voltage characteristics of the peripheral section of the device for all the impurity concentration relations simulated.
Since a positive feedback is formed in the direction to which the current is made to flow in the negative resistance region, current localization is formed, further causing breakdown of the device. Therefore, the current that can be made to flow in the active section before the active section is broken down (the avalanche withstanding capability) is limited by the avalanche voltage (the voltage between the drain and the source), at which negative resistance is formed in the peripheral section. Considering the impurity amount variations, the avalanche withstanding capability of the device having the conventional structure is around 50 A/cm2. See FIG. 28. Therefore, for improving the avalanche withstanding capability within a predetermined impurity amount variation range, it is necessary to improve the avalanche voltage, at which negative resistance is formed in the peripheral section of the device, so that the avalanche voltage in the peripheral section can be equal to or higher than the avalanche voltage in the active section. Alternatively, it is necessary to relax the negative resistance characteristics so that positive resistance characteristics can be obtained.
There remains a need for a semiconductor device without the problems associated with the conventional superjunction semiconductor device. The present invention addresses this need.